5600

000000D44B: -- -- -- 88 11 02 04 A8 │ 00 B4 01 98 0C 78 0E FC €◄☻♦Ё ґ☺˜♀x♫ь
000000D45B: 0F 00 00 00 00 00 00 03 │ 00 08 08 00 18 00 00 3F ☼ ♥ ◘◘ ↑ ?
000000D46B: FC 00 00 00 00 00 00 00 │ 00 00 00 00 00 00 00 29 ь )
000000D47B: 00 00 70 0C 04 62 00 00 │ 08 00 00 00 04 04 00 00 p♀♦b ◘ ♦♦
000000D48B: 00 00 00 00 00 18 00 00 │ 3F FC 00 00 00 00 00 00 ↑ ?ь
000000D49B: 00 00 00 00 00 00 00 00 │ 34 00 00 70 0C 04 62 00 4 p♀♦b
000000D4AB: 0F 08 00 00 00 04 0D 00 │ C0 00 00 00 4D 54 36 31 ☼◘ ♦♪ А MT61
000000D4BB: 4B 32 35 36 4D 33 32 00 │ 00 18 00 00 3F FC 00 00 K256M32 ↑ ?ь
000000D4CB: 00 00 00 00 00 00 00 00 │ 00 00 00 00 33 00 00 70 3 p
000000D4DB: 0C 04 62 01 81 08 00 00 │ 00 04 04 00 C0 00 00 00 ♀♦b☺Ѓ◘ ♦♦ А
000000D4EB: 4B 34 5A 38 30 33 32 35 │ 42 43 00 15 00 00 00 50 K4Z80325BC § P

struct atom_vram_info_header_v2_5 {
struct atom_common_table_header table_header;
uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings
uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings
uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping
uint16_t reserved; // offset of reserved
uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings
uint8_t vram_module_num; // indicate number of VRAM module
uint8_t umcip_min_ver;
uint8_t umcip_max_ver;
uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
};

struct atom_vram_module_v11 {
// Design Specific Values
uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
uint16_t mem_voltage; // mem_voltage
uint16_t vram_module_size; // Size of atom_vram_module_v9
uint8_t ext_memory_id; // Current memory module ID
uint8_t memory_type; // enum of atom_dgpu_vram_type
uint8_t channel_num; // Number of mem. channels supported in this module
uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
uint8_t tunningset_id; // MC phy registers set per.
uint16_t reserved[4]; // reserved
uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
uint8_t vram_flags; // bit0= bankgroup enable
uint8_t vram_rsd2; // reserved
uint16_t gddr6_mr10; // gddr6 mode register10 value
uint16_t gddr6_mr0; // gddr6 mode register0 value
uint16_t gddr6_mr1; // gddr6 mode register1 value
uint16_t gddr6_mr2; // gddr6 mode register2 value
uint16_t gddr6_mr4; // gddr6 mode register4 value
uint16_t gddr6_mr7; // gddr6 mode register7 value
uint16_t gddr6_mr8; // gddr6 mode register8 value
char dram_pnstring[40]; // part number end with '0'.
};

struct atom_vram_module_v10 {
// Design Specific Values
uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not
uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined
uint16_t reserved[3];
uint16_t mem_voltage; // mem_voltage
uint16_t vram_module_size; // Size of atom_vram_module_v9
uint8_t ext_memory_id; // Current memory module ID
uint8_t memory_type; // enum of atom_dgpu_vram_type
uint8_t channel_num; // Number of mem. channels supported in this module
uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
uint8_t tunningset_id; // MC phy registers set per
uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
uint8_t vram_flags; // bit0= bankgroup enable
uint8_t vram_rsd2; // reserved
uint16_t gddr6_mr10; // gddr6 mode register10 value
uint16_t gddr6_mr1; // gddr6 mode register1 value
uint16_t gddr6_mr2; // gddr6 mode register2 value
uint16_t gddr6_mr7; // gddr6 mode register7 value
char dram_pnstring[20]; // part number end with '0'
};

struct atom_vram_info_header_v2_4 {
struct atom_common_table_header table_header;
uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
uint16_t dram_data_remap_tbloffset; // reserved for now
uint16_t reserved; // offset of reserved
uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init
uint16_t vram_rsd2;
uint8_t vram_module_num; // indicate number of VRAM module
uint8_t umcip_min_ver;
uint8_t umcip_max_ver;
uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
};