Hi all,

I prepared a ballout/pinout for GDDR6X memory. The pin labels might not be 100% accurate, but the pins and their types should be accurate. If you nevertheless find errors, please let me know, and I will fix the file.

I hope this is useful for you.

Note that your pin labels are phisical names, not logical (signal naming) names.
Here is the non-colored table labeled with signal naming

Yes, you are right, these are physical labels, and they are surely not applicable to all GPU's. Thank you for sending this map, I will integrate the signal naming into my map soon, then we have both in one.

Hi all,

I have merged Signal labels sent by galkinvv into my ballout map, and have also prepared a flipped version showing everything from the bottom view. Please let me know about other cards for which the physical labels hold true, as well as any errors or inconsistencies you might encounter.

Best Regards,

bd250

Looks great! The is a note about logical names - they combine the single-sided memory mode and double-sided clamshell memory mode (high bits of part A and low bits of part B are disabled in double-sided mode).
In this mode many of memory contacts are NC, and some contacts are GND. The publicly available double-sided MSI v388 RTX 3090 boardview can be used for a reference .

There is 2 notes about them:

• The only extra GNDs in double-sided mode are EDCs - that are pins A10, V5. In the attached file the V5 is marked as GND, but the mark of A10 is forgotten
• Those double-sided mode marks are more related to physical connection than to signal/logical. Maybe those alternatives should be moved to the second row (physical connection).

And the final one. Your work for preparing this diagram is great, and of course it is your decision what to do with it and how to distribute it.
However, distributing it only in pdf form without some "editable source" makes impossible for others to make enhancements in the document. So, if somebody will have an idea about improvements or notes an inconsitency - there would be no simple way to make edit. So, additionally sharing the source form of this diagram can be useful!

I have thought about this, and I think you are right on all 3 issues. Attached you can find a new, updated version with following changes:

• The error on A10 has been corrected

• I have moved all single-side memory mode alternate connections to the physical address labels

• I have added additional information to the notes

• I have included the source file

Perhaps somebody can contribute by creating a second top and bottom view ballout, which is based on physical addresses for cards running in single-side memory mode. I am also hoping that people can give more examples which AMD(future)/NVIDIA cards uses which mode, and whether there are further differences in physical addresses.

I think this would be practical as GDDR6X memory is going to stay with us for quite some time.

Great! Looking at it, I noticed several areas for improvement.
The clock pins. Those are complex. My answer is a bit late since I paused to get a physical de-soldered 8Gbit chip to measure it.

• The physical label info for clock lines from datasheet is a pair of lines, one of them includes an asterisk in the name (FBx_WCKab/*). For all 5 clock pairs, the PCB signal without '*' goes to the "_t" pin, and the PCB signal with '*' goes to the "_c" pin. So I suggest including "*" in the second line of physical markings for K10, С5, C10, T5, T10. For example, "(FBx_WCK45*/NC)" for C10. And for the logical lines for J10, K10 - the upper logical part shouldn't duplicate the physical one. The "CLK/CLK*" included there was just a not-too-clear separation in my markings. So, I suggest marking K10 like
  
  Код: Выделить всё

  CLK_c
(FBx_CLK1*)

• The VSS and SENSE markings for D10, C10, R5, T5 were taken from the datasheetp (picture attached below). It says that for 8Gbit=1GByte memory ICs those pins are not clocks, but power sense outputs. However, electrically measuring the D8BGX IC all those 4 pins seems to be no contact: the resistance is infinity, the parasitic capacitance is 0. They don't look similar to sense pins (other 4 WCK pins have normal measuring with ~300KOhm resistance). Unfortunately, I haven't 16Gbit de-soldered D8BZC/D8BZF chip to measure it. If someone have those chip and is interested - please measure D10, C10, R5, T5 on it, to check if it is more similar to other WCK pins or to no contact.
  
  So I think that their sense markings I suggested earlier looks too theoretic by now, and from practice D10, C10, R5, T5 can be marked like "(not all ICs)" in first of 3 lines, instead of current VSS/SENSE theoretical leftovers, like
  
  Код: Выделить всё

  (not all ICs)
WCK1_c_A
(FBx_WCK45*/NC)


The picture above also gives info on what power pins are VDD and what are FBVDDQ. Each quarter has 4 VDD pins in 6 FBVDDQ pins. Version 3 has a typo: the K2 pin is VDD too.

And a small note about ZQ pins in Versin 3 - removing the "=" symbol and placing the entire "360Ohm to GND" label in second line would make it more readable.

The left-side labelling as numbers is a bit misleading for me, since during "fast look" it is found before the letter-based marking places in center. However, I'm not sure what's the best way to improve it. Maybe letter-based marking duplicated on the left AND on the right, with numeric markings in the center. That way, letter-based markings will be most easily traced from any cell.